Georgia Institute of Technology ECE 6465 Memory Device Technologies and Applications
Professor Shimeng Yu · Georgia Institute of Technology · 9 lectures with notes
Students in this class: ask your lecturer for the class code, and these lectures will already be in your library when you sign up.
Lecture 0 Admin
ECE 6465 connects memory-cell physics and circuit design to mainstream and emerging memory technologies and their industry applications.
Lecture 3 SRAM Part 1
A 6T SRAM cell stores data with cross-coupled inverters, while carefully balanced transistor strengths protect its state during reads.
Lecture 2 CMOS Review and Scaling Part 2
CMOS scaling is moving vertically, from FinFETs to nanosheets and potentially stacked complementary FETs.
Lecture 3 SRAM Part 2
SRAM read speed and stability depend on bitline sensing margin, transistor strength ratios, and increasingly difficult scaling.
Lecture 3 SRAM Part 3
SRAM design balances read stability, writeability, speed, and leakage through circuit assists, alternative cells, and careful layout.
Lecture 3 SRAM Part 4
SRAM miniaturization is constrained both by lithographic patterning and by transistor variability that erodes cell noise margins.
Lecture 3 SRAM Part 5
SRAM scaling trades tighter transistor control and higher density for new variability, soft-error, layout, and thermal challenges.
Lecture 3 DRAM Part 1
DRAM’s density depends on a compact 1T1C cell, while charge sharing and restoration constrain core speed.
Lecture 4 DRAM Part 2
DRAM must trade sensing margin, refresh overhead, retention reliability, and cell density as its technology scales.