Lecture 0 Admin

Overview

Shimeng Yu introduces ECE 6465, Memory Device Technologies and Applications, a graduate course at Georgia Tech focused on memory-cell behavior, array design, technology scaling, and industry trends. The course moves from mainstream SRAM, DRAM, and flash to emerging memories, peripheral-circuit design, and in-memory computing, with learning assessed through problem sets, SPICE labs, and exams.

Key takeaways

ECE 6465 links device-level analysis of memory-cell stability, variability, and reliability to array-level concerns such as sensing, timing, and addressing.
The course compares SRAM, DRAM, and flash with emerging memory technologies, emphasizing both scaling history and current industry direction.
Assessment includes four problem sets worth 5% each, SPICE-based labs worth 30%, and a midterm worth 25%; the grading scheme is curved.
SPICE is the central tool for lab circuit simulations, while some problem sets may require MATLAB; Yu plans a short SPICE tutorial for students who need it.
The course connects memory technology to AI applications through a closing unit on in-memory computing.

Chapters

0:00 ECE 6465 Logistics, Learning Goals, and Prerequisites

Shimeng Yu teaches the three-unit course on Tuesdays and Thursdays from 12:30 to 1:45; office hours are Thursdays at 2 p.m.
Canvas hosts lecture materials, assignments, lab submissions, and the syllabus; recordings from the Fall 2024 offering are available on YouTube.
Students study memory-cell stability, variability, and reliability, then scale from individual cells to arrays with sensing, timing, and addressing circuits.
Recommended preparation includes undergraduate semiconductor device physics and digital-circuit fundamentals, with some analog-circuit knowledge.

7:00 Course Materials, SPICE Labs, Grading, and Submission Policies

There is no required textbook; Yu’s memory book is available through the library, and lecture slides are the primary course materials.
Four problem sets contribute 5% each and may use MATLAB; circuit-simulation labs use SPICE and contribute 30% of the total grade.
The midterm is planned for late October and counts for 25%; exams are closed-book and allow one page of notes, with the final following the registrar’s schedule.
Assignments are submitted as PDF scans through Canvas; late penalties and other grading rules are in the syllabus, and grading questions should be raised within one week of returned work.

12:00 SRAM, DRAM, Flash, Emerging Memories, and Semester Schedule

The technical sequence begins with semiconductor-memory and CMOS-scaling overviews, then examines SRAM, DRAM, and flash as widely commercialized technologies.
For each memory type, the course considers cell operation, stability, variability, scaling, and technology trends.
The later-semester focus shifts to emerging memory technologies under research and development, alongside peripheral-circuit and memory-bank design.
The course concludes with memory applications including in-memory computing; the tentative schedule and midterm timing may change, while the final follows the registrar’s schedule.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Shimeng Yu.