Lecture 13: Arithmetic Building Blocks - Adders

Overview

Binary addition is developed from a one-bit full adder into CMOS implementations and multi-bit architectures, with carry propagation identified as the main source of delay. The lecture compares a 28-transistor baseline, mirror and transmission-gate adders, and carry-bypass, carry-select, and carry-lookahead strategies, explaining tradeoffs in delay, transistor sizing, and circuit complexity.

Key takeaways

A ripple-carry adder's delay scales approximately as (n − 1)Tcarry + Tsum, so carry propagation, not the final sum computation, dominates wide additions.
The one-bit full adder computes S = A XOR B XOR Cᵢ and Cₒ = AB + ACᵢ + BCᵢ; the equivalent generate-propagate form is S = P XOR Cᵢ and Cₒ = G + PCᵢ.
A baseline CMOS full-adder implementation uses about 28 transistors, and long transistor stacks can require larger devices that increase area and capacitance.
A mirror adder exploits self-duality to use more symmetric networks, reduce the maximum series stack from four transistors to about three, and simplify layout.
Carry bypass improves long additions by routing a carry around a group when all its propagate bits are 1, but added multiplexers can make the design slower for narrow adders.
Carry-select and carry-lookahead approaches reduce dependence on serial carry arrival by selecting precomputed outcomes or expanding carry equations using generate and propagate signals.

Chapters

0:00 Data Paths and Word-Level Processing

A simplified digital system separates memory, a processing unit or data path, control, and input/output.
The data path combines registers, adders, shifters, multiplexers, and other units selected for each operation.
Processors typically handle words such as 16, 32, or 64 bits rather than processing one bit at a time.

3:00 From Boolean Expressions to Adder Inputs

Boolean simplification can reduce circuit complexity by factoring common terms, as with an expression such as AB + BC + CA.
For two multi-bit operands A and B, each bit position has corresponding inputs Aᵢ and Bᵢ.
Every bit after the least significant position also receives a carry from the preceding position.

6:00 Defining the One-Bit Full Adder

A full adder accepts three one-bit inputs: A, B, and carry-in Cᵢ.
Its outputs are the sum bit S and carry-out Cₒ, which becomes the next stage's carry-in.
The least significant stage starts with carry-in set to zero.

10:00 Building the Full-Adder Truth Table

The three-input truth table has eight input combinations, covering every value of A, B, and Cᵢ.
Adding 1 + 1 + 1 produces binary 11, so both the sum and carry outputs are 1.
Adding 1 + 1 + 0 produces binary 10, so the sum is 0 and the carry is 1.

14:00 Deriving the Sum Function and XOR Parity

The sum output is the three-input XOR: it is 1 when an odd number of A, B, and Cᵢ inputs are 1.
A two-input XOR is 1 precisely when its inputs differ, represented by AB̅ + A̅B.
Bitwise XOR can compare copied data with original data: matching bits produce 0, while differences flag a mismatch.

17:00 CMOS Implementation of Sum and Carry

The carry function is AB + ACᵢ + BCᵢ, which can be factored as AB + Cᵢ(A + B).
In the NMOS pull-down network, series connections implement products and parallel branches implement sums; the PMOS network is constructed complementarily.
The sum network can reuse the carry output in a modified expression, avoiding a fully separate implementation of the original sum function.

22:00 Why Adder Improvements Matter

Adder performance affects the computing capacity used in applications such as rocket calculations, scientific simulation, and drug discovery.
The lecture connects faster arithmetic circuits to broader gains in computer performance and computational capability.
Circuit research often begins by identifying limitations in a working design and then trading area or complexity for better performance.

28:00 Transistor Count and Series-Stack Costs

The baseline one-bit CMOS full adder uses about 28 transistors.
Four series-connected transistors increase resistance and delay, while intermediate nodes add capacitance-related effects.
To offset series-stack resistance, transistor widths may need to increase substantially, raising layout area.

32:00 Ripple-Carry Adder Connections

A ripple-carry adder connects each stage's carry-out to the next stage's carry-in.
Each stage's sum is an independent result; only the carry propagates through the chain.
An n-bit ripple adder can be assembled by replicating a one-bit full-adder cell and connecting adjacent carry signals.

38:00 Ripple-Carry Delay Grows with Bit Width

If each stage takes Tcarry to produce a carry and Tsum to produce a sum, an n-bit ripple adder takes approximately (n − 1)Tcarry + Tsum.
For a 4-bit adder, the final sum can require three carry delays plus one sum delay.
In a 64-bit adder, the final bit may wait through 63 carry stages, making carry delay the main performance concern.

44:00 Carry Inversion and Alternating Adder Cells

The carry output node can be heavily loaded by diffusion and gate capacitances from the cell and the next stage.
Removing an output inverter can reduce carry-path delay, but the following stage must accept an inverted carry.
The inversion property allows alternating cells to use inverted inputs and outputs so the carry can connect between stages without restoring an inverter at every boundary.

48:00 Inversion Property Trades Area for Carry Speed

Inverting all inputs to the full-adder function also inverts its outputs, enabling carry polarity to alternate across stages.
The approach removes an inverter from the carry path but adds input inverters, including for A and B at affected stages.
The tradeoff increases inverter count while targeting the carry delay that dominates long ripple chains.

54:00 Mirror Adder Uses Symmetric Networks

The mirror-adder topology uses matched NMOS and PMOS network structures rather than strictly complementary pull-up and pull-down layouts.
Its construction relies on the self-dual behavior of the full-adder sum and carry functions.
The symmetry can simplify layout by aligning corresponding transistor gates and sharing routing.

58:00 Self-Dual Boolean Functions Enable the Mirror Adder

A self-dual Boolean function retains its form under the relevant input and output complementation transformation.
The lecture identifies the full-adder sum and carry functions as having the property needed for the mirror topology.
This property allows the mirrored network to implement the intended logic without the usual complementary-network arrangement.

1:04:00 Mirror Adder Reduces Stack Depth and Sizing

The mirror topology limits its longest series stack to about three transistors, compared with four in the earlier design.
The example contrasts transistor sizing factors of roughly 6 with 8 for the larger series-stack case.
Reducing stack depth can improve delay and reduce device area, while symmetric branches also make layout connections more straightforward.

1:09:00 Capacitance on the Mirror-Adder Carry Node

Carry-node loading includes four diffusion capacitances and two internal gate capacitances in the described cell.
The carry output also drives about six gate capacitances in the next adder cell.
The next-stage load helps explain why carry-node capacitance and drive strength are central to adder timing.

1:14:00 Transmission-Gate Full Adder Alternative

A transmission gate pairs NMOS and PMOS transistors so the circuit can pass both logic 0 and logic 1 effectively.
A transmission-gate XOR-based adder is presented as an alternative to the CMOS pull-up/pull-down designs.
The lecture treats this topology as supplementary rather than the primary design approach for the course project.

1:20:00 Generate, Propagate, and Delete Carry Conditions

Generate is defined as G = AB: when both operand bits are 1, the stage creates a carry regardless of carry-in.
Propagate is defined as P = A XOR B: the stage passes the incoming carry through when the operand bits differ.
Delete is defined as A̅B̅: when both operand bits are 0, the stage removes an incoming carry.

1:24:00 Carry Logic from Generate and Propagate Signals

The full-adder equations can be written as S = P XOR Cᵢ and Cₒ = G + PCᵢ.
A CMOS implementation uses the generate and delete conditions to pull the carry output high or low, while the propagate condition connects carry-in to carry-out.
A dynamic-logic variant is also shown; its clock-controlled structure illustrates another implementation style, although the lecture emphasizes the static CMOS designs.

1:30:00 Cascading Full Adders and Using Half Adders

A multi-bit adder is formed by cascading identical one-bit cells, passing each carry-out to the next carry-in.
The least significant stage has no prior carry, so its sum can be computed as A XOR B.
A half adder can replace a full adder at a stage that does not need carry-in, avoiding unnecessary circuitry.

1:36:00 Carry Bypass Adder Adds a Shortcut

A carry-bypass adder retains a ripple path but adds a bypass route controlled by a group propagate signal.
When every bit in a group propagates, the incoming carry can bypass the internal ripple chain.
A multiplexer selects between the bypassed carry and the carry produced by ordinary propagation.

1:40:00 Carry Bypass and Manchester Carry Chains

The bypass condition for a four-bit group is the conjunction of its four propagate signals.
If the group does not propagate the carry, the design falls back to the regular carry chain.
A Manchester carry-chain implementation is introduced as another realization of the carry-bypass principle.

1:44:00 Four-Bit Groups Balance Bypass Benefit and Cost

A system-level example divides a 16-bit adder into four-bit carry-propagation blocks.
Larger groups require wider propagate logic with more series-connected devices, increasing circuit delay and implementation difficulty.
A four-bit group has a 1-in-16 chance of all propagate signals being 1 under the lecture's simple probability model; larger groups make bypass activation less likely.

1:50:00 When Carry Bypass Beats Ripple Carry

A bypass adder can be slower for small bit widths because its extra multiplexer and routing add overhead.
For larger adders, bypassing some ripple stages can reduce total delay compared with waiting for every carry to ripple.
The preferred group size balances the probability of a useful bypass against the delay and area of the added circuitry.

1:53:00 Carry-Select Adder Precomputes Both Outcomes

A carry-select adder computes candidate results for carry-in 0 and carry-in 1 before the incoming carry is known.
A multiplexer selects the correct stored candidate once the carry condition is determined.
Unlike bypassing, carry selection can avoid waiting for a carry to traverse the full chain when the correct candidate can be identified.

1:58:00 Carry-Lookahead Equations Expand the Carry Chain

Starting from Cₖ = Gₖ + PₖCₖ₋₁, repeated substitution expands each later carry into generate terms and products of propagate signals.
For example, C₁ = G₁ + P₁G₀ + P₁P₀Cᵢ, and C₃ includes terms for G₃, P₃G₂, P₃P₂G₁, P₃P₂P₁G₀, and P₃P₂P₁P₀Cᵢ.
The expanded equations motivate carry-lookahead logic that computes carries from generate and propagate conditions rather than waiting for a simple stage-by-stage ripple.

Transcript excerpt

0:00 okay so the first slide is more like a hypothetical view of how things are done in a digital environment so we actually have separate memory block historically again we are heading towards the generation where memory and uh processor will kind of be marged at some point we are trying to go uh towards logic in memory or process in memory but without heading to that uh you know Cutting Edge realm let's just stick to the basics for the time being uh whatever we can use in our day-to-day devices we have a separate memory block and we have a separate Processing Unit which is often mentioned as data path we'll talk about that but we have a separate control block and IO input output right we provide some inputs take in some out

0:48 take out some output and we control the flow of information between the memory block and the processor meaning if you need to do some sort of multiplication you fet the data from the memory block block do that computation and store the output maybe in the memory block again unless you want to just directly show it at the output okay and data path is made out of multiple segments like we have registers we have adders we have shifters multiplexers depending on what you want to do you bring in that memory and provide as input to maybe the adder maybe the shifter maybe the multiplier maybe the register depending on what you want to do with it okay so all of this obviously this is a really high high level simplistic view but just to give you some perspective as to how this data

1:37 path is made up and uh here are some comments uh just to easily explain what these comments are uh we typically do

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