University of South Carolina CSCE 611
Professor Bakos · University of South Carolina · 8 lectures with notes
Students in this class: ask your lecturer for the class code, and these lectures will already be in your library when you sign up.
CSCE 611 Fall 2026 Lecture 1: Introduction
CSCE 611 teaches students to implement and test a RISC-V CPU using SystemVerilog and FPGA design tools.
CSCE 611 Fall 2026 Lecture 2: RISC-V ISA 1
RISC-V assembly fundamentals and fixed-point multiplication prepare students to build an FPGA square-root calculator.
CSCE 611 Fall 2026 Lecture 3: RISC-V ISA 2
Build and test a Q18.14 square-root program in RARS before deploying it on the RISC-V FPGA CPU.
CSCE 611 Fall 2026: Lecture 4: SystemVerilog 1
SystemVerilog models hardware through behavioral logic and reusable structural modules, with simulation and synthesis revealing different aspects of a design.
CSCE 611 Fall 2026 Lecture 5: More SystemVerilog
SystemVerilog’s core design patterns and the FPGA workflow for building Lab 2’s seven-segment decoder.
CSCE 611 Fall 2026 Lecture 6: Even more SystemVerilog
SystemVerilog essentials for FPGA labs: simulation, test benches, combinational logic, and avoiding unintended latches.
CSCE 611 Fall 2026 Lecture 7: SystemVerilog 4
SystemVerilog coding patterns lead into RAM timing and the multiport RISC-V register file.
CSCE 611 Fall 2026 Lecture 8: RISC-V Microarchitecture 1
Jason D. Bakos explains how to build and pipeline a 22-instruction RISC-V CPU in SystemVerilog for Lab 3.