CSCE 611 Fall 2026 Lecture 12: Sequential Logic 2 and Timing Analysis 1

Overview

Jason D. Bakos finishes finite-state-machine design with examples showing that states must represent both output possibilities and input history, then introduces timing analysis for combinational and sequential circuits. He explains AXI’s five independently handshaken channels, contamination and propagation delay, glitches, setup and hold constraints, and a timing example where a 215 ps setup path supports about 4.65 GHz but a 55 ps minimum path violates a 70 ps hold requirement.

Key takeaways

An FSM needs enough states not only to represent its outputs but also to preserve every relevant input context; the elevator’s floor position changes how it responds to the same button.
A serial divisibility-by-three detector needs only three remainder states because each incoming bit updates the remainder as r' = (2r + b) mod 3.
AXI separates address, data, and response traffic across five independently handshaken channels, allowing outstanding requests to tolerate long peripheral latency.
Circuit propagation delay is determined by the longest gate path, while contamination delay is determined by the shortest path; the difference creates a window in which glitches can occur.
For a register-to-register path, setup timing limits the maximum clock rate, but hold timing also imposes a minimum delay, so logic can fail by being too fast.
The worked path has a 215 ps setup budget, implying about 4.65 GHz, but its 55 ps minimum delay fails a 70 ps hold requirement and needs added buffering.

Chapters

0:00 FSM State Counts: Outputs and Remembered Context

Traffic-light outputs require four configurations, while the two-floor elevator needs four states despite only three movement outputs.
Elevator states distinguish which floor the car is on, because the response to a button depends on that context.
A bus requester can use two states to alternate between not requesting and requesting as the grant signal changes.
A modulo-3 counter cycles through three states without inputs and pulses its output once every third cycle.

5:10 Rising-Edge Detection Requires Input History

The edge detector tracks the last two sampled input bits, giving four states for the patterns 00, 01, 10, and 11.
Its output should assert for the 01 pattern, which identifies a transition from zero to one.
A rising-edge detector reacts to sampled values: if input changes on a clock edge, the flip-flop samples the value present just before that edge.
The example’s output pulse appears after the input transition has been sampled into the corresponding state.

11:45 Serial Divisibility by Three with Three Remainder States

A serial binary number can have an unbounded number of bits, so storing the entire value in a fixed-width register cannot solve the problem.
The machine needs only three states, representing the current value’s remainder modulo three.
For each new bit b, the updated remainder is (2r + b) mod 3, since shifting the number left doubles it before adding the bit.
The output indicates divisibility when the current remainder is zero, including the initial empty or zero value.

19:39 Reading Next-State Logic from Flip-Flop Hardware

In the prior final-exam example, Q0 and Q1 are state bits, and the logic feeding each flip-flop defines its next-state function.
The stated Q0 input is A OR Q0 OR Q1; the Q1 input is B OR Q1 OR the output of the preceding OR gate.
The output Z is Q0 AND Q1, and the truth table can be traced across clock cycles.
Because the OR logic feeds back state bits, the state 11 is stable once reached.

22:57 Why CPU Peripherals Use AXI

AXI is a widely used on-chip communication protocol that lets a CPU connect to peripherals through a shared interface standard.
AXI supports long-latency devices such as DRAM and permits outstanding requests, unlike simple protocols that handle one transaction at a time.
A CPU can issue a store using an address, write data, and a write-enable control, then an interface module translates that operation into AXI signals.
Memory-mapped peripherals occupy address blocks, so a CPU’s effective store address selects devices such as USB, DMA, disk, or keyboard controllers.

26:33 AXI’s Five Channels and Valid-Ready Handshakes

AXI separates traffic into read-address, write-address, read-data, write-data, and response channels.
Each channel uses its own valid-ready handshake, allowing address acceptance, data transfer, and acknowledgements to occur independently.
For a write, the master presents the address with valid until the receiver asserts ready, then later presents write data through the separate data channel.
The B response channel returns the write acknowledgement, while a simple teaching implementation may support only one transaction at a time.

30:14 An AXI Write Adapter as a State Machine

A CPU-facing adapter can accept a store address and data, then step through AXI address, data, and response phases.
A busy signal applies back pressure to the CPU while the adapter completes the transaction; an error flag can report a failed operation.
The adapter’s finite-state machine mirrors the phases of the AXI write timing diagram.
The same address-based connection supports memory-mapped I/O, even though the address may identify a peripheral rather than RAM.

34:36 Timing Specifications and Simulation Epsilon Delay

A combinational circuit has a timing specification describing how long output changes take after input changes; sequential circuits are often evaluated by their maximum clock frequency, fmax.
Behavioral SystemVerilog simulation abstracts away physical gate delay, though nonblocking assignments schedule updates after a simulation event.
Physical FPGA or chip implementations have nonzero delays determined by the underlying technology.
Testbenches commonly add a small delay before checking outputs so they observe scheduled simulation updates.

38:15 Contamination Delay, Propagation Delay, and Critical Paths

Contamination delay, tCD, is the earliest an output can begin changing; propagation delay, tPD, is the latest time by which it settles.
Gate delays vary with output transition direction and conditions such as chip temperature.
Circuit-level tPD is the sum of gate propagation delays along the critical, longest path; circuit-level tCD comes from the shortest path.
The example contrasts a three-gate path from some inputs with a one-gate path from another input.

42:00 Counting Logic Paths and Explaining Output Glitches

For the illustrated four-input, two-output, three-gate circuit, path counts are propagated by labeling each input 1 and summing labels at gate outputs, yielding seven paths.
Changing one input can move the circuit between two truth-table rows that both specify output 1, yet unequal path delays can briefly drive the output low.
In the example, two inputs to a final OR gate transition from 01 to 10 at different times, creating a temporary 00 and a glitch.
Glitches occur during the uncertainty interval between contamination and propagation delay.

48:49 Karnaugh-Map Redundancy and Clock-Speed Motivation

A redundant consensus term can bridge adjacent Karnaugh-map groupings and prevent the illustrated combinational hazard.
That extra logic preserves the Boolean function while eliminating the glitch, though the hazard is often harmless in synchronous designs.
For sequential systems, the main timing goal is usually to keep register-to-register paths within the clock period.
Bakos identifies branch resolution as a likely critical path in the course CPU because it combines register reads, ALU comparison, control logic, and PC selection.

52:31 Flip-Flop Delays, Setup Time, and Aperture

A flip-flop’s clock-to-Q propagation and contamination delays are technology parameters, denoted tPCQ and tCCQ.
The D input must be stable before the active clock edge for the setup time and remain stable afterward for the hold time.
Setup and hold together define the aperture interval during which the input must not change.
Designers mainly control the combinational logic between registers; FPGA tools use technology-library data to check whether paths meet timing.

1:01:18 Setup and Hold Checks: The 215 ps Example

The setup constraint requires clock period to cover clock-to-Q propagation, combinational-path propagation, and the receiving flip-flop’s setup time.
In the example, 50 ps clock-to-Q plus 105 ps through three gates plus 60 ps setup totals 215 ps, corresponding to a maximum frequency of about 4.65 GHz.
The shortest path has 25 ps circuit contamination delay; adding 30 ps clock-to-Q contamination gives 55 ps, less than the 70 ps hold requirement.
Buffers can lengthen short paths to fix hold violations, while setup failures may require a slower clock or a redesigned pipeline; CAD tools attempt hold repair automatically.

Transcript excerpt

0:00 So today we're going to I'm going to finish up the sequential logic lecture and then we'll try to get through the uh the next lecture on timing analysis. So uh we went through this example with the academic avenue and bravado boulevard and we implemented the design at the gate level. Although as I mentioned you don't the synthesizer will take care of this for you in in uh uh in our case in the lab. Um um then I had this other example from one of the exams several years ago. This was a elevator example where the elevator can be on um the first

0:49 floor or the second floor and then you can you know you can call the elevator with the buttons outside um or you can you know move the elevator by hitting the buttons inside. And so I showed the uh state the state machine for that. So the question here is how many um how many states do we need given the problem? So in the in the traffic light example there was there were four possible configurations of the traffic lights right? We had a green light on academic or a green light on bravado and then you could have a yellow light on academic or a yellow light on bravado. So that's four configurations, output value configurations. And so we had four, we just happen to have four states, right? Um, and so you need to have at least one

1:37 state for every output possibility at least in a more machine where you associate the outputs with states. You also need to have a state and and this is the second condition is the one that's a little bit um it makes it difficult to design state machines sometimes. You also need a state for

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Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Jason D. Bakos.