CSCE 611 Fall 2026: Lecture 4: SystemVerilog 1

Overview

Jason D. Bakos reviews RISC-V exam problems, then introduces SystemVerilog as a hardware description language for representing, simulating, and synthesizing circuits. The lecture distinguishes behavioral and structural designs, explains abstraction, hierarchy, regularity, combinational and sequential logic, and covers practical SystemVerilog concepts including four-state logic, waveforms, propagation delay, synthesis, and module connections.

Key takeaways

RISC-V pseudo-instructions are assembler conveniences: `li x1, 5` becomes `addi x1, x0, 5`, and `jr x2` becomes `jalr x0, x2, 0`.
A loop that shifts one bit per iteration and decrements a count of three executes nine dynamic instructions; a variable `sll` performs the same shift in one instruction.
A 32-bit Q29.3 encoding of 9.125 stores the scaled integer 9.125 × 8 = 73, represented as hexadecimal `0x49`.
SystemVerilog hierarchy and regularity make designs easier to understand and reuse, but synthesis flattens modules into a circuit and can obscure source-level signal names during JTAG debugging.
SystemVerilog’s `X` can mean either an unknown/conflicting simulation value or an intentional don't-care assignment, while `Z` represents high impedance.
Behavioral simulation abstracts away physical gate delays; waveform debugging still requires tracing signal values over time and accounting for scheduled output updates.

Chapters

0:00 RISC-V Pseudo-Instructions, Jumps, and Branch Counting

The pseudo-instruction `li x1, 5` assembles to `addi x1, x0, 5`; RISC-V `jr x2` is a pseudo-instruction for `jalr x0, x2, 0`.
A branch to a nearby label can assemble as `jal x0, offset`, using PC-relative addressing and discarding the link address in `x0`.
The example loop decrements `x1` and branches while it is greater than or equal to zero, so the branch is taken five times for values 4 through 0.
Conditional branches express `if` and loop tests; a compiler may combine a conditional branch with an unconditional jump to implement a `for` loop.

10:30 Midterm RISC-V Questions: Shift Loops and Fixed-Point Values

A three-instruction loop repeatedly shifts `x2` left by one bit and decrements `x3` until `x3` reaches zero; with `x3 = 3`, it executes nine instructions.
The loop can be replaced by the single variable-shift instruction `sll x2, x2, x3` when the architecture supports that operation.
For a 32-bit Q29.3 representation of 9.125, the fractional portion 0.125 is 1/8, so the scaled integer is 73, or hexadecimal `0x49`.
The exam review distinguishes static instruction listings from dynamic execution counts and notes that a separate pipeline-stall question requires material not yet covered.

18:15 Behavioral, Structural, and Physical Hardware Representations

Behavioral descriptions specify a circuit’s function, such as a Boolean expression, arithmetic operation, or finite-state machine.
Structural descriptions show components and their connections; physical representations include ASIC layout polygons or FPGA placement and routing.
A SystemVerilog addition of two 8-bit switch inputs into an 18-bit result can synthesize into many lower-level adder components.
Synthesized schematics are useful for sanity checks and critical-path investigation, but large designs often produce unwieldy diagrams.

24:15 SystemVerilog Can Describe Both Behavior and Structure

An `assign` statement identifies behavioral code by describing a logic result rather than manually instantiating gates.
Structural Verilog can instantiate modules such as an AND gate and inverter, then connect them through named signals.
Designs commonly use structural code at higher levels to connect modules and behavioral descriptions for lower-level components.
Module reuse matters: outlining a short expression as its own module adds instantiation and wiring overhead unless the component is reused.

26:29 VHDL and Verilog: Origins and Industry Use

VHDL was developed for the U.S. Department of Defense to specify chip behavior more precisely than English prose; its name expands from VHSIC Hardware Description Language.
VHDL began as a description language, then gained simulation and synthesis tools; its syntax is verbose, case-insensitive, and influenced by Pascal and Ada.
Verilog emerged in industry in 1984 with case-sensitive syntax more familiar to C programmers; SystemVerilog is the language used in this course.
Bakos characterizes VHDL as more common in universities and Verilog as more common in industry, motivating the course’s switch to Verilog.

31:10 Abstraction Across the Hardware Design Stack

Software relies on an operating system, an operating system relies on a processor architecture, and an architecture relies on a microarchitecture.
Microarchitecture designers use logic cells such as AND gates and flip-flops without redesigning their transistor implementations.
Technology libraries provide reusable cell libraries; lower-level design can continue from logic gates to transistor circuits and semiconductor physics.
Abstraction lets each design layer assume that details beneath it are handled by the next layer.

35:08 Hierarchy Builds Complex Circuits from Reusable Modules

A one-bit full adder can be combined into a multi-bit adder, which can support a subtractor, comparator, or part of a floating-point unit.
SystemVerilog modules can be nested to keep components understandable and reusable, often with each module small enough to inspect on a screen.
Synthesis tools flatten the hierarchy into a circuit; the hierarchy is a design aid, not a physical organization preserved on the chip.
Flattening can complicate FPGA debugging because JTAG probes may expose optimized signal names rather than the hierarchy’s original names.

39:20 Regularity: Choose Modules That Can Be Reused

Hierarchy is a design choice: a complete CPU could be written in one large module, but that makes code harder to navigate and debug.
Outlining extracts a code region into a separate module; inlining replaces a module or function call with its contents.
Regularity favors components that can be instantiated repeatedly, such as full adders or floating-point functional units.
Reusable modules reduce repeated design work and make large circuits feasible to describe with comparatively little source code.

42:10 Logic Circuits as Modules with Interfaces and Specifications

A logic circuit has input and output ports, a functional specification, and a timing specification such as latency in cycles or nanoseconds.
A SystemVerilog module resembles a class interface: external ports are visible to other modules, while internal wires and components remain inside.
Combinational logic outputs depend on current inputs; sequential logic outputs can also depend on prior input history.
Exhaustively testing an n-bit combinational input requires checking 2^n combinations, while sequential behavior adds possible histories of inputs.

48:37 Combinational Circuits, Feedback, and Wire Contention

A CPU’s ALU is combinational, while state-holding components such as the program counter are sequential.
A combinational circuit should not contain feedback cycles; cross-coupled asynchronous circuits can introduce difficult race conditions.
A signal may fan out from one gate output to multiple inputs, but connecting two active outputs to the same net can create contention.
In schematics, a T-junction indicates connection; crossing wires are connected when a junction dot marks the crossing.

51:38 Synthesizable SystemVerilog and the Logic Data Type

SystemVerilog supports simulation-oriented code as well as synthesizable code; only a restricted subset can be converted into hardware.
The `logic` data type is the primary synthesizable signal type covered here, representing one bit unless declared as a packed range.
A multi-bit register is represented as an array or vector of `logic` bits rather than a high-level integer or floating-point value.
SystemVerilog modules can include constructs that are useful for test benches but cannot become circuit gates.

1:00:52 Four-State Logic: 0, 1, X, and Z

SystemVerilog `logic` has four simulation values: `0`, `1`, `X`, and `Z`, rather than only binary zero and one.
An uninitialized flip-flop or RAM location appears as `X` in simulation, making the unknown state visible instead of choosing a random value.
A conflicting double-driven signal can resolve to `X`; if both drivers agree on zero or one, the conflict may not be apparent.
Setting a signal to `X` in code can express a don't-care condition for optimization, while `Z` represents a high-impedance, undriven state.

1:02:18 Simulation, Synthesis, and Reading SystemVerilog Waveforms

The two main uses of SystemVerilog code are simulation, which tests behavior, and synthesis, which compiles a design into gates.
A module with inputs `a`, `b`, and `c` and output `y` can describe a Boolean expression using an `assign` statement.
A test bench supplies input stimulus; a waveform displays signal values over time and can show all 2^3 input combinations for three input bits.
To debug a waveform, place or move the time cursor and inspect the values of each signal at the point where the design begins to fail.

1:07:43 Propagation Delay and Synthesis Optimization

Physical gates have nonzero propagation delay because wires and gate inputs have resistance and capacitance; the RC time constant relates resistance and capacitance to delay.
A behavioral simulation abstracts away technology-specific timing, so an output may appear to change at the same displayed time as its input.
Event-driven simulation may schedule an output update after an epsilon delay, meaning a value read at the exact input-change instant can still be the old value.
Synthesis can minimize Boolean logic: a circuit’s gate-level result may differ from the literal structure implied by the original expression while preserving its function.

1:12:24 SystemVerilog Syntax, Ports, and Module Instantiation

SystemVerilog is case-sensitive, ignores whitespace, disallows names that begin with numbers, and uses C/Java-style comments.
Ports define module inputs and outputs; named connections map a parent signal such as `n1` to a child module’s output port such as `y`.
A structural parent module can instantiate a behavioral child, establishing design hierarchy through the instance and its port mapping.
After flattening, parent and child names can refer to the same physical wire, so JTAG tools may expose only one of the source-level names.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Jason D. Bakos.