CSCE 611 Fall 2026 Lecture 3: RISC-V ISA 2

Overview

Jason D. Bakos reviews the RISC-V instruction subset for CSCE 611 labs, then develops the Q18.14 fixed-point square-root algorithm students will test in RARS before deploying it on an FPGA CPU. The lecture explains 64-bit multiplication and cross-register shifting, binary-search convergence, switch and display scaling, and practical input constraints that make tested software essential before hardware integration.

Key takeaways

Q18.14 multiplication produces 28 fractional bits, so restoring a 14-bit fractional format requires a 14-bit right shift across the combined 64-bit product, implemented with two shifts and an OR.
Binary search provides a square-root method using only multiplication and comparisons, making it suitable for the course CPU without division hardware.
The 18 FPGA switches encode an integer; shifting their value left by 14 converts it to Q18.14, and the same scale factor converts displayed raw results back to real numbers.
RARS’s signed 32-bit input limit requires entering upper-half unsigned raw values as R − 2³², especially for switch inputs of at least 2¹⁷ after Q18.14 scaling.
Testing the fixed-point program in RARS before integrating it with the FPGA CPU makes later failures easier to attribute to hardware rather than unverified software.

Chapters

0:00 RISC-V Instruction Groups and the Lab 1 Subset

The CPU labs focus on six instruction categories: register operations, immediate operations, branches and jumps, loads and stores, and coprocessor instructions.
Register operations include arithmetic, AND/OR/XOR, shifts, and comparisons; RISC-V branches also provide signed and unsigned comparisons directly.
Students should restrict Lab 1 code to the listed supported subset so the program can later run on the CPU built in Labs 3 and 4.

4:00 Multiply Instructions, Branches, and Jump-and-Link Pseudoinstructions

RISC-V MUL returns the low 32 bits of a product, while high-product variants provide upper bits for signed or unsigned multiplication.
Branch comparisons include equality, inequality, and signed or unsigned greater-than-or-equal and less-than; reversed operands can express less-than-or-equal conditions.
An unconditional jump pseudoinstruction such as `j` assembles as `jal x0, target`, discarding the return address; `jal` defaults to `x1` when a link register is needed.

8:00 12-Bit Immediates and Constructing Constants with LUI

Most RISC-V immediate instructions use a signed 12-bit value, from −2048 through 2047.
The U-type `lui` instruction places a 20-bit immediate in a register’s upper bits; an additional instruction supplies the low portion of a larger constant.
RARS expands large-constant pseudoinstructions into multiple machine instructions, illustrating how a value such as 429,496,730 cannot fit in one 12-bit immediate.

11:00 Fixed-Point Numbers as a Low-Cost Alternative to Floating Point

Fixed point represents fractions with integers and an implied scale of 2⁻ᶠ, where f is the number of fractional bits; two fractional bits, for example, scale an integer by one quarter.
Addition and subtraction require operands to use the same fractional-bit format, while multiplication adds the operands’ fractional-bit counts.
Lab 1 uses 14 fractional bits, so squaring a value in that format produces 28 fractional bits and requires rescaling.

15:00 Recovering Both Halves of a 32-Bit Fixed-Point Product

Multiplying two 32-bit operands can produce a 64-bit result; RISC-V combines `mul` with a high-product instruction to recover both halves.
Bakos demonstrates fixed-point decimal-digit extraction by multiplying by a 32-fractional-bit representation of 0.1, then rescaling the fractional remainder by 10.
The example is assembled and run in RARS; entering 4567 produces the reversed digits 7654, and a large constant is visibly expanded into multiple instructions.

23:00 Rescaling Q18.14 Products Across Two Registers

The FPGA calculator uses Q18.14: 18 whole-number bits and 14 fractional bits in a 32-bit value.
Squaring a Q18.14 value yields 28 fractional bits across the 64-bit product, so the result must shift right by 14 places to restore the desired format.
Because RISC-V operates on 32-bit registers, the cross-register shift is assembled with three operations: shift the low half right 14, shift the high half left 18, then OR the pieces together.

29:00 Square-Root Approximation with Binary Search

The square-root routine searches for x such that x² matches the input, avoiding Newton–Raphson because the teaching CPU does not implement division.
It compares each squared guess with the input, adjusts the guess up or down, and halves the step size after each iteration.
With 14 fractional bits, the representable resolution is 2⁻¹⁴, approximately 1/16,384; some inputs reach an exact zero error while others stop at the format’s precision limit.

35:00 Mapping Q18.14 Values to FPGA Switches and Displays

The board’s 18 switches provide an integer input, while the square-root routine uses a 32-bit Q18.14 value internally.
The program shifts the switch value left by 14 bits to create the fixed-point input; the hex displays can show the fractional result.
For RARS testing, an actual input such as 5.5 must be encoded by multiplying it by 2¹⁴; decode an output by dividing its raw value by 2¹⁴.

40:00 RARS Test Vectors and Spreadsheet-Based Debugging

Bakos recommends a downloadable spreadsheet that traces each binary-search guess, its square, the error, and decimal and hexadecimal raw values.
The search begins with guess zero and a step of 256, half the approximate maximum root of 512 for an 18-bit switch input.
Lab test cases pair the raw integer entered in RARS with the expected raw result; inputs such as zero and 16,384 test square roots of 0 and 1 respectively.

46:00 Handling RARS Signed Input for High Unsigned Values

RARS’s integer-input system call accepts signed 32-bit values, so raw values above 2³¹−1 cannot be entered as positive decimal integers.
For a desired unsigned raw value R in the upper half of the 32-bit range, enter R − 2³² instead; the resulting bit pattern is the intended unsigned value.
The constraint appears when an 18-bit switch input is shifted left by 14: inputs at or above 2¹⁷ produce raw values whose top bit is set.

52:00 Lab 1 Validation and Installing the Course RARS Build

Lab 1’s tested square-root program becomes part of the later CPU test suite, separating software defects from hardware defects during integration.
The course provides a modified RARS build with support for its custom CSRRW-based I/O instructions; stock GitHub RARS may not recognize those instructions.
On Linux, launch the downloaded Java archive with `java -jar` and the RARS filename; RARS is also available for Windows and macOS.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Jason D. Bakos.