CSCE 611 Fall 2026 Lecture 11: Sequential Logic 1

Overview

Jason D. Bakos reviews the CSCE 611 midterm, including RISC-V jump-and-link behavior, fixed-point ranges, SystemVerilog testbenches, and pipelined CPU control signals, then introduces synchronous sequential logic and finite-state-machine design. A four-state traffic-light controller demonstrates Moore outputs, next-state tables, state encoding, and a three-process SystemVerilog implementation; bus requests, elevator control, counters, and edge detection provide further examples.

Key takeaways

In RISC-V, `jal` writes the address after the jump into its link register; corrupting that stored return address can make `jalr` target an invalid instruction location.
A fixed-point value with 10 fractional bits has a resolution of 2^-10; using a signed 32-bit representation gives an approximate range from -2^21 to 2^21 - 2^-10.
A Moore FSM separates state storage from combinational next-state and output logic; in SystemVerilog this naturally maps to one `always_ff` block and separate `always_comb` blocks.
For the four-state traffic controller, two state bits suffice, and unconditional transitions through yellow states enforce a one-clock-cycle yellow interval.
Synchronous design should place at least one register in every cyclic path, preventing combinational feedback such as an unregistered stall signal loop.
The teaching CPU cannot directly load or store RAM because it lacks a data-memory interface, even though its `CSRRW` GPIO output could be adapted into a constrained external-memory workaround.

Chapters

0:00 Midterm Scores and RISC-V Jump-and-Link Execution Trace

The midterm mean was 57.5 out of 80, or 72%, and the median was 59, or 74%; 5 of 55 students earned perfect scores.
The grade distribution included 29% in the A range and 24% in the F range; Bakos plans to consider a course curve after project grades are included.
In the program trace, `jal` to `deck` stores the return address `C` in `x1`, while `x2` is decremented before `jalr x1` returns to the loop.
The final register values are `x1 = C` and `x2 = 0`, and the execution sequence terminates at address 18.

1:29 Return-Address Corruption and Fixed-Point Precision

Changing the instruction at address 10 to `addi x1, x1, -1` changes the return address from `C` to `B`.
Address `B` is not a valid instruction address in the example, so the corrupted `jalr` target causes invalid control flow.
Fixed-point formats divide a bit vector into integer and fractional bits; neural processing units still use fixed-point arithmetic.
Accuracy of 2^-10 requires 10 fractional bits; with a signed 32-bit value, the range is approximately -2^21 through 2^21 - 2^-10.

9:40 SystemVerilog Adder Testbench and Output Checking

A `tester` module instantiates the combinational `adder` module and connects its inputs and output to local signals.
Driving inputs with 10 and 11 should produce 21, which is hexadecimal `15`.
Use an `initial` block or continuous assignments to drive inputs, then wait before checking the output so combinational propagation can complete.
A mismatch can be reported with `$display` or another observable test action; 25 of 55 students received full credit.

14:32 Request-Grant Handshaking, Bitwise XOR, and Pipeline Delay

The request-grant behavior can be understood as request following the complement of grant with a one-clock-cycle delay.
For a three-bit input, bitwise XOR with `101` flips bits 2 and 0 while leaving bit 1 unchanged; it does not reduce the vector to one bit.
The logic path from `in_val` through registers A and B to output C imposes two clock cycles of delay.
The review reports 32 of 55 full-credit responses on the request-grant problem and 29 of 55 on the XOR truth table.

23:05 CPU Datapath Controls Across Execute and Writeback

The ALU second-input mux selects either a register operand or a sign-extended immediate, distinguishing R-type from I-type operations.
`ALUOpEx` specifies the ALU operation, while `reg_write_EX` and GPIO write enable describe execute-stage intent.
A GPIO-writing instruction sets GPIO write enable rather than register write; register select and ALU source can be don't-cares when their datapaths are unused.
An `addi` operand typo made one control-signal case ambiguous; Bakos said students should receive credit for either interpretation of that case.

35:27 Why the Teaching CPU Cannot Directly Load or Store Data

The CPU design has no data memory or data-memory address and data paths, so it does not directly support conventional load and store instructions.
`Load upper immediate` has the word load in its name but does not transfer data between RAM and registers.
The `CSRRW` GPIO output could be repurposed with external logic as a limited memory interface, though the design lacks a normal address path.
Bakos accepted some alternative answers because GPIO-based memory emulation is technically possible, while the expected answer was no data-memory support.

38:55 Combinational Logic, Sequential Logic, and Stored State

Combinational outputs depend only on current inputs and are described with `assign`, `always_comb`, or legacy `always @*`.
Sequential outputs depend on input history, which requires memory and can be described using `always_ff` or `always_latch`.
Synchronous sequential logic updates state using a clock; asynchronous sequential logic reacts to input changes but is vulnerable to glitches and instability.
Latches are level-sensitive and flip-flops are edge-sensitive; flip-flops are generally preferred in FPGA designs because latches complicate timing analysis.

42:47 Synchronous Design Rules and Traffic-Light Controller Setup

A synchronous design uses registers and combinational logic, has at least one register, and clocks its registers from the same clock.
Every cyclic path should contain a register; for example, a register prevents a control-unit stall signal from forming a combinational loop.
The traffic-light example has detectors `TA` and `TB`, lights for Academic Avenue and Bravado Boulevard, a clock, and reset.
The clock period is chosen to equal the yellow-light duration, making a one-cycle yellow state a useful design assumption.

46:17 Four Moore States for the Academic and Bravado Lights

The controller needs four states: Academic green with Bravado red, Academic yellow with Bravado red, Bravado green with Academic red, and Bravado yellow with Academic red.
In a Moore machine, outputs depend only on the current state and therefore change with state transitions on clock edges.
A Mealy machine places outputs on transitions, allowing outputs to depend directly on inputs; Bakos focuses on Moore machines in this course.
Traffic-light transitions keep a road green while its detector reports traffic, then pass through yellow before granting green to the other road.

50:38 Deriving the Traffic-Light Next-State Table and Encoding

Each transition in the state diagram becomes a next-state table row, with current state and detector inputs determining the next state.
In state S0, no Academic traffic advances to S1, while Academic traffic loops in S0; Bravado traffic is a don't-care for this decision.
Yellow states S1 and S3 transition unconditionally to the opposite road's green state, so each lasts one clock cycle.
Four states require at least two bits; the example encodes S0 through S3 as `00`, `01`, `10`, and `11` before deriving Boolean next-state logic.

54:09 SystemVerilog FSM Structure: State Register and Combinational Logic

Synthesis tools derive state encodings and Boolean logic, so the designer can describe transitions rather than hand-build the gate-level truth table.
A Moore machine uses separate logic for next state and outputs; output logic depends on the current state, not directly on traffic inputs.
SystemVerilog supports enumerated state types with syntax such as `typedef enum logic [1:0]`, followed by declarations for current and next state.
The state-register `always_ff` block resets to S0 or assigns `current_state <= next_state` on each clock; separate `always_comb` blocks implement transitions and light outputs.

1:01:50 Clocked State Timing and Bus-Request FSM Examples

An asynchronous reset changes the state immediately, while normal state updates occur at rising clock edges; flip-flop propagation delay appears after each edge.
Next-state logic is combinational and can react to detector changes between clock edges, but the current state waits for the next edge.
The midterm request-grant behavior can be modeled with two states, not requesting and requesting, with transitions governed by grant.
A two-floor elevator example uses four states: stopped on floor 1, moving up, stopped on floor 2, and moving down.

1:07:05 Modulo-3 Counter, Rising-Edge Detection, and Quiz Schedule

A book example uses three enumerated states and unconditional case transitions to implement a modulo-3 counter, with an output pulse when the state is S1.
A rising-edge detector must distinguish a prior zero from a transition to one; the lecture's four-state example remains unfinished as class time runs out.
Bakos says the sequential-logic lecture will continue the following week and that Quiz 4 covers state machines.
Quiz 4 was already live and due the following Friday; Quiz 3 had been missed because it was not unlocked.

Transcript excerpt

0:00 The mean score was 57.5, which is 72%. Median was 59, which is 74. Um the distribution is was fairly typical in this course. It's a little frustrating because, you know, you expect there to be a normal sort of bell distribution. Um but in this class it tends to be more of a kind of a beta distribution where you have um a large population that does really well and then you have sort of a uniform population across, you know, spanning from spanning the whole range. Have a little bit of a normal Gaussian here around 55 to 60. So, we had five students that got

0:47 perfect scores, which is 9%. Uh 29% were in the A range, 9% were in the B range, 20 were in the C range, 16 in the D range, and 24 in the F range. Yeah, so the problem is it's um I'm not sure. I'd like to um curve this somehow, but it's really hard to do because just because of the distribution. So, I think we'll apply the curve after at the end of the semester because uh in this class generally the project scores are very high that offset the, you know, the exam scores. Uh so, I just want to go through these real quick just so everyone's on the same page. Um so, question one gave a program and

1:35 asked some questions about it. So, the first thing you want to do is well, you don't have to do this, but um you can create a symbol table which associates these these symbols, these these these these these labels with addresses. So, we have three addresses in here. We've got loop, which is at four, uh deck, which is at 10 and hex and exit which is 18.

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Related notes

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Jason D. Bakos.