CSCE 611 Fall 2026 Lecture 5: More SystemVerilog

Overview

Jason D. Bakos explains SystemVerilog’s module hierarchy, port connections, concurrent assignments, vector operations, and conditional expressions, emphasizing how behavioral descriptions become hardware and how to avoid multiple drivers and combinational loops. He then details CSCE 611 Lab 2: build a seven-segment decoder, connect eight instances to an FPGA’s 18 switches and displays, and use the supplied project skeleton and scripts to simulate and program the board.

Key takeaways

SystemVerilog modules combine a defined port interface with internal behavior, and named connections such as `.Y(N1)` make hierarchical wiring explicit.
Continuous assignments and module instances describe concurrent hardware rather than sequential software execution; source order does not schedule circuit behavior.
Every driven signal should have a single owner, and circular combinational dependencies can prevent a simulator from settling; a register boundary can break the loop.
Vector operations act bitwise across corresponding positions, while slicing, concatenation, and replication support tasks such as extending a signed RISC-V immediate to 32 bits.
The FPGA’s seven-segment outputs are active-low and individually connected: zero lights a segment, with 56 segment signals across eight displays.
Lab 2’s 18 switches provide four full four-bit hexadecimal inputs plus a two-bit partial input, so three of the eight display inputs must be tied to zero.

Chapters

0:00 SystemVerilog Modules, Ports, and Continuous Assignments

A module packages an interface and internal behavior; organizing modules hierarchically can express large circuits with relatively little code.
The example module declares inputs A, B, and C and output Y; ports of the same direction and type can share a declaration.
The `assign` statement describes combinational behavior, and its right-hand-side signals determine when the output may need to update.
Treat each output as having one driver: assigning Y from multiple sources can create conflicting hardware drivers.

8:00 Reading Logic Waveforms as Time-Indexed Truth Tables

A simulator waveform plots signals against time, with each vertical slice showing the inputs and corresponding output at one instant.
The example test pattern cycles A, B, and C through all eight three-bit combinations, allowing Y to be checked against the Boolean function.
The testbench supplies the changing inputs; the module under test only computes the output.
Behavioral simulation shows logical behavior, not physical propagation delay from FPGA or ASIC resistance and capacitance.

14:00 Synthesis, Gate-Level Equivalence, and SystemVerilog Style

Synthesis converts behavioral code into an equivalent gate-level circuit; the resulting schematic need not mirror the written Boolean expression gate for gate.
Jason D. Bakos notes that SystemVerilog is widely used in industry, while VHDL remains common in academia; learning one makes learning the other easier.
SystemVerilog is case-sensitive, ignores whitespace, and uses C- and Java-style comments.
The language has syntax peculiarities, including a semicolon after a module header and packed-vector declarations.

16:00 Hierarchical Designs and Named Port Connections

A top-level module can instantiate a leaf module; instance names such as `ANDgate` help identify components during simulation.
Named port connections use `.formal_port(actual_signal)`, for example connecting a child module’s Y output to parent signal N1.
In the NAND3 example, an AND3 instance drives internal signal N1, which then feeds an inverter whose output connects to the top-level Y.
One physical net can appear under different names in different scopes, such as N1 in the parent and Y or A inside child modules.

25:08 Concurrent Hardware Semantics and Explicit Number Literals

Structural module instances and continuous assignments describe concurrent circuits, so swapping their source-code order generally does not change behavior.
Signal declarations must appear before use in the shown coding style, even though connected circuit statements are not executed sequentially like software.
Sized literals use a width, apostrophe, base, and value, as in `8'b11` for the value 3 represented in eight bits.
Specify literal widths and bases explicitly to make intended hardware sizing clear; unsized values are commonly treated as decimal and default to 32 bits.

28:04 Packed Logic Vectors and Bitwise Operations

A declaration such as `logic [3:0] A` creates a four-bit signal with indices 3 through 0; the range appears before the signal name.
A shared declaration such as `input logic [3:0] A, B` applies the direction, type, and width to both ports.
Bitwise operators apply independently to corresponding bits, so a four-bit AND operation represents four parallel one-bit AND operations.
The schematic may display vector-wide connections and gates even though the implementation consists of individual bit-level logic.

34:00 Ternary Expressions for Multiplexers and Combinational Dependencies

The ternary form `condition ? true_value : false_value` naturally describes a two-input multiplexer controlled by the condition.
Bakos connects muxes to CPU datapaths, where control signals select sources such as a register or immediate, or choose ALU versus memory data.
Dependent continuous assignments trigger chains of updates; circular dependencies can cause a combinational loop and simulator convergence failure.
For the pipeline branch-stall example, inserting a bubble into the current stage can make the control logic oscillate; placing a register boundary breaks the feedback loop.

40:20 Operator Precedence, Shifts, and Hardware-Cost Considerations

SystemVerilog includes Boolean, arithmetic, comparison, shift, and conditional operators, including dedicated NAND and XNOR-style operators.
Logical and arithmetic shifts differ in how right shifts fill vacated bits; SystemVerilog uses distinct operators for the two behaviors.
Multiplication and division can imply costly hardware, and a combinational single-cycle divider was too large for the course FPGA’s CPU design.
The course’s ALU includes multiplication but omits division because of that hardware cost.

44:15 Bit Slices, Concatenation, Replication, and Sign Extension

Indexing a vector selects one bit, while a range such as `A[2:1]` extracts a multi-bit slice.
Concatenation uses braces and commas to join signals into a wider value; replication uses nested braces, as in a three-copy form of one bit.
Sign extension copies the most significant sign bit into the newly added high-order positions before concatenating the original value.
A RISC-V 12-bit signed immediate must be extended to the 32-bit ALU width; the lecture also compares this with MIPS’s 16-bit immediate.

51:12 Reduction Operators and Ternary-Based Lookup Tables

Reduction operators combine all bits of a vector into one result, such as using an AND reduction to form an eight-input AND; XOR and related reductions are also available.
Nested ternary expressions can implement a lookup table by matching an input value to a constant output.
The seven-segment decoder example maps a four-bit input to seven output bits across 16 possible input values.
Bakos presents the ternary-table approach as suitable for the decoder, but not for the CPU control unit’s more complex logic.

53:57 Lab 2: Build and Instantiate a Seven-Segment Decoder

Lab 2 introduces SystemVerilog by implementing a combinational circuit and deploying it to an FPGA board.
The decoder maps a four-bit value to a seven-bit pattern so each display can show hexadecimal digits 0 through F.
Students implement one decoder module and instantiate eight copies, preparing the design to display CPU outputs in Lab 3.
The board has 18 switches: four complete nibbles, a fifth display controlled by two switches, and three displays that must be tied to zero for this lab.

59:02 FPGA Display Wiring, Constraint Names, and Active-Low Outputs

The board has eight seven-segment displays with 56 individually connected segments; they are continuously driven rather than multiplexed.
The synthesized top-level module’s port names must match the FPGA constraint file’s names so toolchain pin mappings reach the intended board components.
Display outputs are named `hex0` through `hex7`, each carrying seven segment bits; segment 0 is at the top, numbering proceeds clockwise, and segment 6 is the middle.
Display segments are active-low: output 0 lights a segment and output 1 turns it off; the 18-bit switch input is named `SW` and switches read 0 when down and 1 when up.

1:04:54 Project Skeleton, FPGA Test Pattern, and CSCE 611 Scripts

The supplied tar.gz project skeleton includes `top.sv`, the mostly empty `hex_driver.sv`, and `simtop.sv` for simulation.
Students connect the 18-bit switch input to eight hex-driver instances and route their seven-bit outputs to the eight display ports.
A clocked LED heartbeat in `top.sv` provides a toolchain sanity check; the Lab 2 decoder itself is combinational and does not require a clock.
The `csce611.sh` script supports `testbench`, `program`, and `pack`; packing excludes or removes intermediate build files to keep submissions under Blackboard’s 25 MB limit.

1:10:00 Monday Quiz, Lab 2 Schedule, and the Jump to Lab 3

A multiple-choice quiz on SystemVerilog, with possible RISC-V material, is due before Monday’s class; it is open-book, untimed, and allows two attempts.
The Lab 2 sheet contains requirements, a grading rubric, and instructions, while the skeleton supplies the needed project files.
Lab 2 is expected to be straightforward and due in about two weeks; Lab 3 is a substantial difficulty jump because it requires a working CPU.
Bakos says testing the CPU as isolated pieces such as only a register file or ALU has proved difficult, motivating the larger integrated Lab 3 assignment.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Jason D. Bakos.