EE 2115 - Lec 22 - 2026_10_16

Overview

Hiren Trada connects first-order RC frequency filtering to pulse-delay design, then combines an RC network with comparators to delay rectangular pulses while preserving their logic shape. The lecture derives 75%/25% hysteresis thresholds, illustrates a 110 kΩ–1.3 nF delay circuit with a 143 μs time constant and LTspice, and extends the hysteretic-comparator design into a self-oscillating square-wave generator.

Key takeaways

In a series RC circuit, output across the resistor is high-pass behavior, while output across the capacitor is low-pass behavior; the time constant τ = RC sets the relevant transition scale.
An RC network alone turns pulse edges into exponential ramps; a comparator restores sharp transitions, and comparator thresholds determine the added delay.
Positive feedback gives a comparator hysteresis, separating its rising and falling thresholds and reducing ambiguous switching as the capacitor voltage changes.
For a 0–4 V pulse and a 75% threshold, the capacitor must reach 3 V; with τ = 143 μs, the exponential charging equation predicts the threshold-crossing delay.
A hysteretic comparator with its output fed back through an RC network becomes an oscillator: the capacitor alternates between two thresholds and generates a continuous square-like waveform.
Real designs should check the comparator datasheet for input current and propagation delay; the intended RC delay must dominate the comparator's own delay.

Chapters

0:00 RC Frequency Filtering: DC Blocking and Signal Applications

Pulse delays can protect equipment from inrush current and stagger industrial motor startup after a power restoration.
Electronic filters select signals by frequency, such as a phone receiver isolating Verizon from nearby AT&T and T-Mobile transmissions.
For a series RC circuit, a capacitor eventually blocks steady-state DC current; the output across the resistor is therefore zero.

6:00 RC High-Pass and Low-Pass Behavior

Taking output across the resistor makes the RC circuit a high-pass filter; taking output across the capacitor makes it a low-pass filter.
The time constant is τ = RC, and the comparison between τ and a signal's period helps determine how its frequency components appear at the outputs.
Simple RC filters can divide woofer and tweeter signals in inexpensive two-way speaker crossover networks.

12:00 Pulse Delay Architecture: RC Network and Comparator

The design goal is to delay a square-wave or rectangular-pulse transition without changing the pulse's duty cycle.
An RC network creates gradual exponential voltage transitions, and a comparator converts those ramps back into a digital-like output.
The initial comparator example uses a half-VCC reference and requires an input pulse long enough relative to the RC time constant.

15:00 Hysteresis Adds Separate Switching Thresholds

A comparator reference at 50% of VCC provides a midpoint for detecting the capacitor's rising and falling voltage.
Positive feedback creates a hysteresis window, with separate high and low switching thresholds; the example describes thresholds near 90% and 10%.
The capacitor must cross a threshold before the comparator switches, inserting a delay between the input pulse and output transition.

20:00 Designing an Inverting Comparator for 75%/25% Thresholds

The worked hysteresis design uses an inverting comparator with positive feedback, switching at 75% of VCC while rising and 25% while falling.
A half-VCC bias and the feedback voltage both affect the comparator input, so the threshold calculation accounts for both contributions.
A 200 kΩ–200 kΩ divider generates half of VCC; its 100 kΩ Thevenin resistance matches the equivalent resistance used in the feedback network.

27:00 LTspice Pulse-Delay Example and RC Timing Calculation

The demonstrated delay network uses a 110 kΩ resistor and a 1.3 nF capacitor, giving τ = 143 μs.
With a 0–4 V input pulse, the 75% threshold is 3 V; the exponential charging equation can be rearranged to calculate when the capacitor reaches that level.
LTspice shows the delayed, inverted output transitions, with calculated transition times of about 198 μs and 184 μs because charging and discharging are asymmetric.

33:00 Turning the Comparator Circuit into an RC Oscillator

Feeding a hysteretic comparator's output back through an RC network creates an oscillator that needs no external signal input beyond its VCC supply.
The capacitor repeatedly charges and discharges between the hysteresis thresholds, causing the comparator output to alternate between high and low.
The high and low durations are derived separately from the RC exponential response using threshold voltages V1 and V2.

36:00 Oscillator Timing Equations and LTspice Verification

For the charging interval, the capacitor rises from V1 toward VCC; for the discharging interval, it falls from V2 toward zero.
Adding the two threshold-crossing intervals gives the oscillation period; symmetric threshold swings produce equal high and low durations.
The LTspice example uses a 10 kΩ resistor, a 1.3 nF capacitor, and 200 kΩ divider resistors to generate a roughly symmetric waveform, with simulation measurements close to the calculations.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Hiren Trada.