Introduction to Logic Circuit Design (University of Utah) - Arithmetic Circuits (Lecture 11)

Overview

Lecture 11 completes binary-coded decimal (BCD) addition and introduces unsigned and signed binary multiplication. It derives the BCD correction condition and compares a multiplexer-based add-six correction with a more compact logic implementation, then builds multipliers from shifts, partial products, half adders, and two’s-complement sign extension.

Key takeaways

A BCD digit uses four bits, but only values 0000 through 1001 represent decimal digits; sums above nine require adding 0110 to produce a valid digit and carry.
A BCD correction detector can use the sum’s carry-out and high-order bits to identify sums greater than nine, avoiding a full comparison against decimal ten.
When the BCD correction constant is fixed at six, the correction condition can be incorporated into adder logic instead of selecting between correction inputs with a separate multiplexer.
Unsigned binary multiplication is implemented as AND-generated partial products shifted according to multiplier-bit position, then combined with half adders and further adder stages.
In two’s-complement multiplication, sign extension repeats the sign bit to increase operand width without changing its represented value.
A right shift by one position yields the integer quotient after division by two, while the discarded least significant bit records whether the original value was odd.

Chapters

0:00 Lecture 11 Roadmap, BCD Addition and Arithmetic Multipliers

The lecture finishes Chapter 3 on number representation and arithmetic circuits, then begins the next combinational-circuit material.
The main topics are completing a BCD adder and constructing multipliers from adder circuits.
Course announcements include a Sunday 11:59 p.m. homework deadline and a Thursday quiz scheduled to start at 3:40 p.m.

4:00 BCD Encodes Each Decimal Digit with Four Bits

Binary-coded decimal assigns a separate four-bit binary code to each decimal digit.
A multi-digit decimal value is represented by concatenating digit codes, not by converting the whole value into ordinary binary.
BCD addition therefore needs a correction step when a four-bit digit sum is not a valid decimal digit.

8:00 BCD Adder Architecture Checks Each Digit Sum

The design first adds the two four-bit BCD digits, including any carry-in from the previous decimal position.
A detector checks whether the binary sum exceeds nine or produces a carry-out.
When correction is required, adding six converts the invalid four-bit result into the correct BCD digit and decimal carry.

10:00 Deriving the BCD Correction Detector

The detector can be derived by listing four-bit results from 10 through 15 and identifying shared input conditions.
The carry-out provides an immediate indication that the sum exceeded the four-bit range.
When there is no carry-out, the high-order sum bits help identify values greater than nine.

17:50 Replacing the BCD Correction Multiplexer with Logic

A straightforward circuit uses a multiplexer to choose between adding zero and adding six to the digit sum.
Because the correction value is specifically six, the correction-control signal can be integrated into the bit-adder logic.
The optimized design avoids a separate multiplexer and reduces the correction hardware, although its logic is less visually intuitive.

29:40 Binary Shifts Multiply or Divide by Two

Shifting an unsigned binary number one position left multiplies its value by two, analogous to multiplying a decimal number by ten when shifting a decimal place.
For example, the lecture uses shifts to show 6 becoming 12 and 10 becoming 20.
A one-place right shift gives the integer quotient after division by two and discards the least significant bit, which may represent a remainder.

34:50 Binary Long Multiplication Forms Shifted Partial Products

Binary multiplication follows the same place-value method as hand multiplication: multiply by each multiplier bit, shift the resulting row, then add the rows.
Each partial-product bit comes from an AND of one bit from each operand.
The least significant product position can be written directly when no other partial-product row contributes to it.

38:00 Two-Bit Multiplier Uses AND Gates and Half Adders

For two-bit operands, the circuit generates bit products such as a0b0, a1b0, a0b1, and a1b1 with AND gates.
The overlapping partial-product columns are summed with half adders, producing product bits and carry signals.
The multiplier structure is derived from the partial-product arithmetic rather than memorized as a fixed diagram.

42:30 Scaling Partial-Product Arrays to Wider Multipliers

A four-bit multiplier extends the same triangular pattern of shifted partial products used in the two-bit example.
Each column combines partial-product bits and incoming carries through additional adders.
The final circuit is hierarchical: bit multipliers create partial products, and adder stages combine them into the full product.

43:50 Signed Multiplication Requires Two’s-Complement Sign Extension

Unsigned multiplication assumes positive operands; signed values in this lecture use two’s-complement representation.
Operands with unequal widths must be extended to a common width while preserving their signed value.
Sign extension repeats the sign bit in the new most significant positions, preserving the number’s two’s-complement interpretation.

50:40 Signed Product Rows, Alignment, and Final Practice

The signed multiplication procedure aligns partial-product rows by place value, including implied zeros at the least significant end.
The rows are added using ordinary binary addition; the bit patterns are handled arithmetically while their interpretation remains two’s complement.
The closing practice emphasizes extending operands correctly, shifting rows as required, and not treating an intermediate carry-out as an extra product bit.

Transcript excerpt

0:50 ‏Good afternoon everyone. I hope you all are doing well. ‏Today we have our lecture 11 and hopefully we gna finish chapter 3 our number representation and arithmetic circuit and we are going to start chapter four which is combinational circuit and it's not too much different with what we have been talking but just a little bit different flavors chapter is the last chapter for your and after that we start completely ‏new types of circuits. All right. So today we gna finish up our binary coded decimal add that we have been working on that in the last lecture. We

1:37 going to finish it and we gna see how the arithmetic multipliers look like. ‏We going to use our others to build multipliers which are more complicated and then we can use multipliers for designing more complicated functions. Regarding announcement homework deadline would be this upcoming Sunday at 11:59 pm quiz one is graded. Please take a look into that try to be as generous as possible for the grading. ‏I mean that part was exactly in our slides. That quiz was exactly in our slides. So please make sure you go over all of our lecture materials, the discussion sessions practice homework the other resources

2:26 that we have on campus from previous from other universities questions and also book. It has many examples. Make sure that you go over them and you practice enough. ‏If you have any questions regarding quiz please let me know and you have one week for requesting if you quiz two would be in two days on Thursday we gna start sharp at 340 pm the material is what we had talked before would be lecture 1 to with more emphasis on lecture 4 to basically car and mostly homework ‏materiales variabl variabl variabl

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