EE 330 Lecture 2026 10 13 Ch5 MOS#4

Overview

The lecture reviews NMOS and PMOS operating-region equations, then applies them to DC-bias design problems by assuming a region, solving for currents and voltages, and checking the result against the saturation or triode condition. Examples cover resistor selection, diode-connected MOSFETs, a matched-transistor current mirror, and a triode-region design; several numerical results in the spoken work appear inconsistent with the stated inputs.

Key takeaways

For an NMOS, saturation requires VDS ≥ VGS − VTN; solving under a guessed region is only valid after checking this inequality against the computed operating point.
A conducting NMOS with its drain tied to its gate is in saturation because VDS = VGS, which is necessarily greater than the overdrive VGS − VTN.
Matched NMOS devices with common gate and source voltages carry equal saturation currents, forming the basic current-mirror relationship; the example’s 32 μA mirror requires about 0.2 V minimum output voltage.
A saturation assumption can be disproved by circuit constraints: with RD = 13.1 kΩ, the predicted current would make the drain voltage negative, so the correct model is triode operation.
The ±1 V bias example’s stated ID = 0.1 mA and VD = 0.2 V imply RD = 8 kΩ, not the 4 kΩ reported during the calculation.
The final design reports W/L = 14.4, but that number should be independently checked because it does not appear to follow from the stated triode equation, 1 mA current, 0.05 V drain voltage, and 0.5 mA/V² process parameter.

Chapters

0:00 NMOS and PMOS Equations for Cutoff, Saturation, and Triode

An NMOS conducts when VGS > VTN; saturation requires VDS ≥ VGS − VTN, while triode operation has VDS < VGS − VTN.
For a PMOS, the corresponding turn-on and saturation checks use VSG > |VTP| and VSD ≥ VSG − |VTP|.
The lecture reviews square-law saturation current and the triode equation, including the optional channel-length modulation output resistance rO.

4:10 Example 5.3: Select RD and RS for a 0.2 mA NMOS Bias

Given VDD = 1 V, VD = 0.2 V, ID = 0.2 mA, VTN = 0.5 V, K′n = 0.4 mA/V², and W/L = 30, the drain resistor is RD = 4 kΩ.
Assuming saturation gives an overdrive of about 0.18 V, VGS ≈ 0.68 V, and VS ≈ −0.68 V with the gate grounded.
The resulting source resistor is about 1.6 kΩ; VDS ≈ 0.88 V exceeds the 0.18 V overdrive, confirming saturation.

13:54 Example 5.4: A Drain-to-Gate Connection Guarantees Saturation

When an NMOS drain is tied directly to its gate, VDS = VGS.
For an on-state transistor, VGS is greater than VGS − VTN, so the saturation condition is automatically satisfied.
The current therefore follows the saturation square law as a function of the tied drain-and-gate voltage and threshold voltage.

18:18 Exercise 5.9: Find the Current and Resistor in a Diode-Connected NMOS

The drain-to-gate connection places the transistor in saturation when it is conducting, allowing ID to be calculated from the saturation equation.
Using K′n = 0.4 mA/V², W/L = 4, and a 0.2 V overdrive gives ID = 32 μA.
With a 1.8 V supply and VD = 0.7 V, the series resistor is about 34.4 kΩ; changing it to 10 kΩ raises the calculated drain voltage to about 1.48 V.

25:29 Exercise 5.10: Matched NMOS Devices Form a Current Mirror

Matched transistors Q1 and Q2 share gate and source voltages, and have the same device parameters, so their saturation currents match.
Q1 is diode-connected; its gate voltage sets Q2’s VGS, making Q2’s current mirror Q1’s current while Q2 remains saturated.
For a 32 μA mirrored current and 1.8 V supply, Q2 needs at least about 0.2 V drain-source voltage; the corresponding maximum load resistor is about 50 kΩ.

33:30 Example 5.5: A Gate Tied to 2 V Produces Triode Operation

With the source grounded, gate at 2 V, VTN = 0.5 V, and drain at 0.1 V, VGS = 2 V and the overdrive is 1.5 V.
Because VDS = 0.1 V is less than the 1.5 V overdrive, the transistor operates in triode; using Kn = 2 mA/V² gives ID ≈ 0.29 mA.
The drain resistor is about 6.55 kΩ, and the MOSFET’s DC ratio VD/ID is about 345 Ω at this operating point.

39:30 Exercise 5.11: Doubling RD Forces a Triode-Region Calculation

Doubling the prior drain resistor to 13.1 kΩ makes a saturation-current assumption predict an impossible negative drain voltage, so the saturation assumption is rejected.
In triode, the lecture forms ID = 3VDS − VDS² in mA for Kn = 2 mA/V² and 1.5 V overdrive, then combines it with ID = (2 − VDS)/13.1.
The physically valid solution is approximately VDS = 0.05 V and ID = 0.15 mA; the other quadratic root is not a feasible operating point.

48:51 Bias Design with ±1 V Supplies: Determine RD from the Drain Target

A new NMOS circuit has its gate grounded, drain fed from +1 V through RD, and source connected to −1 V through RS.
The stated target values include ID = 0.1 mA, VD = 0.2 V, VTN = 0.2 V, K′n = 0.4 mA/V², and W/L = 8.
The lecture applies RD = (VDD − VD)/ID, but its spoken 4 kΩ result conflicts with those stated values, which yield 8 kΩ.

53:00 Calculate RS and Verify Saturation for the ±1 V Circuit

Assuming saturation with ID = 0.1 mA and K′n(W/L) = 3.2 mA/V² gives an overdrive of 0.25 V.
Adding VTN = 0.2 V gives VGS = 0.45 V; with the gate grounded, VS = −0.45 V and RS = (VS − (−1 V))/ID = 5.5 kΩ.
The resulting VDS is about 0.65 V, greater than the 0.25 V overdrive, so the saturation assumption is consistent.

57:27 Final Design Problem: Identify the Region from VGS and VDS

The final circuit has a grounded source, a 1.3 V gate input, a 0.4 V threshold, and a specified output voltage of 50 mV.
Since VGS = 1.3 V, the NMOS is on; its overdrive is 0.9 V.
With VDS = VO = 0.05 V, the device is in triode because VDS is below the overdrive.

1:00:02 Use the Specified 50 Ω Drain-Source Resistance to Find ID

The problem specifies an on-resistance RDS = 50 Ω at VO = 0.05 V.
Ohm’s law gives ID = VDS/RDS = 0.05/50 = 1 mA.
That current can be substituted into the triode equation to solve for the required W/L ratio.

1:03:07 Solve the Final Circuit’s Resistor and Width-to-Length Ratio

With VDD = 1.3 V, VO = 0.05 V, and ID = 1 mA, the series resistor is R = (1.3 − 0.05)/1 mA = 1.25 kΩ.
The lecture reports a required W/L ratio of 14.4 for the final MOSFET design.
That reported ratio appears inconsistent with the stated triode equation and parameters, so it should be checked against the original problem statement.

1:06:30 Wrap-Up: Verify the Region Before Accepting a DC-Bias Solution

The examples repeatedly use a provisional saturation or triode assumption, then test it using VDS versus VGS − VTN.
The next lecture is set to continue with more difficult MOSFET DC-bias variations.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Wireless Power Transfer.