EE 330 Lecture 2026/10/08 Ch5 MOS#3

Overview

The lecture develops a practical method for analyzing PMOS and NMOS transistors: translate PMOS voltage and threshold conventions, check cutoff/triode/saturation conditions, then use the matching current equation. Worked examples cover PMOS gate-voltage ranges, NMOS drain-current curves, and extracting threshold voltage and gain from measurements; the lecture closes with Moore's law, MOSFET scaling, and short-channel/depletion-mode behavior.

Key takeaways

For PMOS calculations, use VSG, VSD, and |VTP|; the device turns on when VSG > |VTP|, and the region boundary is set by comparing VSD with VSG − |VTP|.
In the PMOS example with VS = 3 V, VD = 1 V, and |VTP| = 0.5 V, the device is off for VG ≥ 2.5 V, in saturation for 0.5 V ≤ VG < 2.5 V, and in triode for VG < 0.5 V.
For an NMOS with VTN = 0.5 V and VDS = 1 V, the gate-voltage sweep is off at VG ≤ 0.5 V, saturation from 0.5 V to 1.5 V, and triode above 1.5 V.
Two saturation-region current measurements can determine both K and VTN: form two current equations, divide to eliminate K, solve for threshold, and substitute back.
MOSFET scaling reduces channel dimensions and oxide thickness, but the resulting increase in transistor density makes power consumption and heat removal increasingly important constraints.
A short-channel or depletion-mode device may conduct at zero gate voltage; turning a normally-on device off can require applying a negative gate bias.

Chapters

0:00 PMOS Conventions: Reversing Voltage Subscripts and Threshold Sign

PMOS analysis uses source-referenced voltages VSG and VSD, where NMOS analysis commonly uses VGS and VDS.
Use the magnitude of the negative PMOS threshold, |VTP|, when calculating overdrive.
The PMOS equations mirror the NMOS equations after applying these voltage and threshold substitutions.

2:00 PMOS Triode and Saturation Conditions

A PMOS turns on when VSG exceeds |VTP|; its overdrive is VSG − |VTP|.
Compare VSD with overdrive to identify the operating region: VSD below overdrive indicates triode, while VSD at or above overdrive indicates saturation.
Use the corresponding PMOS current equation with KP and the PMOS voltage conventions; distinguish KP′ from KP when the device dimensions are already included.

10:00 PMOS Example: Classifying Operation as Gate Voltage Changes

For a PMOS with source at 3 V, drain at 1 V, and VTP = −0.5 V, VSD is 2 V and |VTP| is 0.5 V.
The transistor is off when VG is at or above 2.5 V, because VSG no longer exceeds the threshold magnitude.
As VG decreases, the device conducts; the region boundary occurs at VG = 0.5 V, giving triode operation below that point and saturation between 0.5 V and 2.5 V.

21:00 PMOS Gate-Voltage Limits and Current Calculations

With a PMOS source at 1.8 V and |VTP| = 0.5 V, conduction requires VG < 1.3 V.
To distinguish triode from saturation, compare VSD with VSG − |VTP| rather than stopping after checking whether the device is on.
For a specified saturation current, solve the saturation equation for overdrive, then use the gate and drain voltage relationships to find the unknown voltages.
When channel-length modulation is included, use λ to find VA = 1/λ and estimate output resistance with ro = VA/ID.

28:00 NMOS Drain Current as a Function of Gate Voltage

The example uses VTN = 0.5 V and VDS = 1 V to sketch ID versus VG.
For VG at or below 0.5 V, the NMOS is off; above threshold, its overdrive is VG − VTN.
At the 1 V drain voltage, the saturation-to-triode boundary occurs at VG = 1.5 V: the device is in saturation below that boundary and triode above it.
The resulting ID–VG curve is piecewise: zero below threshold, a quadratic saturation segment, and a triode segment at higher gate voltage.

37:00 Using Source-Referenced Voltages When the Source Is Grounded

When the NMOS source is grounded, VGS equals VG, so either notation gives the same numerical value.
If the source is not grounded, calculate VGS as VG − VS rather than treating the gate voltage alone as the controlling voltage.
The plotted curve is an alternative view of MOSFET behavior to the more familiar ID-versus-VDS curves.

39:00 Extracting NMOS Gain and Threshold from Two Measurements

The example gives measured drain currents of 360 μA at VGS = VDS = 1 V and 160 μA at VGS = VDS = 0.8 V.
For a positive threshold, both measurement points are in saturation because VDS exceeds the overdrive VGS − VTN.
Substitute each measurement into the saturation-current equation to form two equations for the unknown device gain K and threshold VTN.
Divide the equations to eliminate K, solve for VTN, and then substitute back to calculate K.

46:00 A Repeatable MOSFET Problem-Solving Checklist

First check whether VGS exceeds VTN for NMOS or VSG exceeds |VTP| for PMOS; otherwise the transistor is off.
For an on-state device, compare VDS or VSD with overdrive to choose the triode or saturation equation.
Track whether a problem supplies K′ or K, and keep current and voltage units consistent when substituting values.
The lecture schedules further worked MOSFET examples before the course moves on to BJTs; the next Tuesday class is online, and the exam is scheduled for October 29.

50:00 From Vacuum Tubes to MOSFET-Dominated Integrated Circuits

The lecture sketches the progression from vacuum tubes to BJTs and then MOSFETs, whose manufacturing became stable enough for integrated circuits around the late 1960s and early 1970s.
MOSFETs became dominant in computer chips; the lecture estimates that more than 90% of transistors in contemporary chips are MOSFETs.
Moore's law is presented as an approximate doubling of transistor density every 18 months, producing an enormous compounded increase over roughly 56 years.

55:00 MOSFET Scaling: Channel Dimensions, Oxide, and Power

Scaling reduces channel length L, channel width W, and gate-oxide thickness together to make devices smaller.
The lecture also describes reducing threshold voltage and supply voltage as device dimensions shrink.
More transistors per chip raise power and heat concerns: electrical power becomes heat, making cooling a major constraint in data centers.
The lecture notes that continued Moore's-law scaling is limited by nanoscale manufacturing and power-density challenges.

59:00 Short-Channel MOSFETs and Normally-On Behavior

Shortening the MOSFET channel can increase current, but also affects electric fields and breakdown behavior.
The lecture contrasts the usual threshold-like ID–VG curve with a short-channel case that can conduct even at zero gate voltage.
A device that conducts without applied gate voltage is normally on; turning it off may require a negative gate voltage.

1:02:00 Depletion-Mode MOSFETs and Final Region Checks

The normally-on behavior is connected to depletion-mode MOSFET operation, in which a negative gate bias can deplete the channel and turn conduction off.
The basic triode-versus-saturation classification still depends on comparing drain voltage with overdrive.
The lecture ends by emphasizing that MOSFET exercises vary the known quantities, but repeatedly use the same region checks and equations.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Wireless Power Transfer.