University of Toronto ECE 1756 FPGA Architecture and Reconfigurable Computing
Professor Vaughn Betz · University of Toronto · 7 lectures with notes
Students in this class: ask your lecturer for the class code, and these lectures will already be in your library when you sign up.
ECE1756_lecture4_part2_2026_compute_device_comparison
FPGAs trade ASIC-level efficiency for flexibility, but can outperform programmable processors on highly parallel streaming workloads.
ECE1756_lecture4_part1_2026_compute_device_comparison
Choosing a compute device means matching the workload to its tradeoffs in throughput, latency, power, and programming effort.
ece1756_lecture3_part2_compute_models_continued
Choose FPGA compute models by balancing control complexity, data movement, throughput, and hardware reuse.
ece1756_lecture3_part1_2026_compute_models_continued
FPGA retiming and time-multiplexing techniques improve clock speed and aggregate throughput while preserving stream behavior.
ECE1756_lecture2_part2_2026_compute_models
FPGA dataflow models trade hardware efficiency for tolerance of variable rates, latency, and runtime reconfiguration.
ECE1756_lecture5_part1_2026_benchmarking_datacenter_fpgas_nn_inference
Fair accelerator benchmarks require optimized baselines; Microsoft Catapult shows how FPGAs can scale across data centers.
ECE1756_lecture5_part2_2026_benchmarking_datacenter_fpgas_and_nn_inference
FPGAs suit low-latency inference when custom precision, memory, and dataflow are more valuable than GPU-scale batching.