Lecture 5 FLASH Part 1

Overview

Shimeng Yu introduces flash as nonvolatile storage, tracing semiconductor memory from one-time-programmable ROM through EEPROM to Toshiba engineer Fujio Masuoka’s 1980s flash invention and the shift from planar scaling to 3D NAND. He explains floating-gate charge storage, derives how stored charge shifts threshold voltage, estimates gate and drain coupling at 0.83 and 0.12, and compares Fowler–Nordheim tunneling with hot-electron programming.

Key takeaways

A floating-gate flash cell stores data as electrons isolated in a gate stack; their negative charge raises the transistor’s threshold voltage and creates a readable separation between erased and programmed states.
The lecture’s capacitive model estimates a gate-coupling ratio of about 0.83 and drain coupling of about 0.12, so control-gate voltage has the stronger influence on floating-gate potential.
Fowler–Nordheim tunneling uses a high electric field to thin an otherwise thick oxide barrier, enabling charge transfer during program or erase while preserving charge during ordinary retention.
Flash oxide must combine extremely low leakage, approximately 10^-16 A/cm² for decade-scale retention, with large program currents during short pulses.
Channel hot-electron programming redirects only about one electron in a million to one in a hundred million into the gate, making its programming efficiency much lower than the total channel current suggests.

Chapters

0:00 Flash as Nonvolatile Storage: Products and Storage Media

Flash retains files without power and appears in SSDs, USB thumb drives, and other storage products.
SATA SSDs preserve compatibility with hard-drive interfaces, while NVMe over PCIe supports higher I/O bandwidth.
Storage technologies include magnetic media such as tape and HDDs, optical media such as CDs and DVDs, and semiconductor memory.

6:00 From OTP ROM to Flash, and SSD Versus HDD Tradeoffs

One-time-programmable ROM stores bits using fuse or antifuse structures, including metal links that are permanently opened by high current.
EPROM introduced UV-light erasure, while EEPROM enabled electrical erasure and reprogramming.
SSDs offer faster startup and access than mechanical 7,200-RPM HDDs, but HDDs remain much cheaper per bit and are used for archiving.

12:00 Floating-Gate Origins, Fujio Masuoka, and Flash Scaling

A floating-gate patent associated with Dawon Kahng and Simon Min Sze described storing charge on an electrically isolated gate.
Toshiba engineer Fujio Masuoka invented modern flash memory in 1984; the technology began with planar NAND and NOR designs.
Planar flash scaled from roughly 1.5 micrometers to below 20 nanometers, reaching a 1Z-class node near 15 nanometers and about 128 gigabits per chip before 3D NAND took over.

18:00 NAND Market, Manufacturers, and the Floating-Gate Transistor

NAND accounts for roughly 95 to 97 percent of the flash market, serving smartphones, enterprise SSDs, USB drives, and SD cards.
Major suppliers include Samsung, SK hynix, Micron, Kioxia, SanDisk, and China’s YMTC; SK hynix acquired Intel’s NAND business, later branded Solidigm.
A planar floating-gate transistor adds an isolated charge-storage gate to a MOSFET, with polysilicon gates and oxide layers.

24:00 How Floating-Gate Charge Encodes Erased and Programmed States

The tunnel oxide separates the floating gate from the channel, while the interpoly dielectric isolates it from the control gate.
The erased state has few stored electrons and a lower threshold voltage; programming adds electrons and raises the threshold voltage.
A read voltage between the two threshold distributions lets a sense amplifier distinguish the high-current erased state from the low-current programmed state.

30:00 Capacitive Coupling Model for the Floating-Gate Voltage

The floating gate couples to the control gate through capacitance CK and to the channel, source, and drain through other capacitances.
With source and drain grounded, total capacitance CT determines how much of the externally applied control-gate voltage reaches the floating gate.
The floating-gate voltage includes both a capacitive-coupling term and a contribution from stored charge, QFG.

35:00 Stored Charge Sets the Flash Memory Window

The gate-coupling ratio is alphaCG = CK/CT, describing the fraction of control-gate voltage coupled to the floating gate.
Comparing programmed and erased states gives a threshold shift proportional to stored charge, with delta VT = QFG/CK in the lecture’s model.
Increasing stored charge widens the threshold-voltage separation, improving the memory window and read-sensing margin.

40:00 Measuring Gate Coupling from Flash and Dummy MOSFET Curves

Yu compares a floating-gate transistor with a dimension-matched dummy MOSFET to estimate coupling from ID–VG curves.
Near threshold, a tenfold current change corresponds to about 1.2 volts of control-gate change for the flash device and about 1.0 volt in the dummy structure.
The measured gate-coupling ratio is approximately 0.83, so a 1-volt control-gate change produces about a 0.83-volt floating-gate change.

45:00 Drain Coupling and the Role of the Control Gate

At higher drain bias, drain-to-floating-gate capacitive coupling must be included alongside control-gate coupling.
Comparing curves measured at drain voltages of 0.1 and 2 volts yields an estimated drain-coupling coefficient of about 0.12.
The smaller drain coefficient is desirable because the control gate should dominate the floating-gate voltage during operation.

50:00 Flash Programming and Erasure: Hot Electrons and Tunneling

Channel hot-electron programming applies a high control-gate voltage, around 12 volts, and a substantial drain voltage, around 5 volts.
Fowler–Nordheim tunneling moves electrons through the tunnel oxide under a strong electric field, with high gate voltage and little or no drain current.
Erase can remove floating-gate electrons through source-side or channel Fowler–Nordheim tunneling by reversing the applied field.

55:00 Fowler–Nordheim Tunneling Through the Flash Tunnel Oxide

A high applied voltage bends the oxide energy bands into a triangular barrier, making tunneling possible even when the oxide is about 8 nanometers thick.
Fowler–Nordheim tunneling current depends exponentially on electric field, making it highly sensitive to voltage.
For silicon and silicon dioxide, electrons face a lower tunneling barrier, about 3.1 eV, than holes, about 3.8 eV.

1:00:00 Fowler–Nordheim Versus Direct Tunneling

Fowler–Nordheim tunneling uses a strong field to create a triangular barrier in relatively thick flash oxide.
Direct tunneling crosses a thin, roughly 2-nanometer barrier and is an unwanted leakage mechanism in logic transistors.
Flash needs a thick barrier during data retention but permits tunneling during brief program or erase pulses.

1:05:00 Retention, Programming Current, and the Charge of About 100 Electrons

Flash must suppress tunnel-oxide leakage to around 10^-16 A/cm² to support roughly 10-year data retention.
A programming pulse can last about 1 microsecond; using a 40-by-40-nanometer gate-area example, Yu estimates that roughly 100 electrons can produce a substantial threshold shift.
The oxide must span about 16 orders of magnitude in current between near-zero-bias retention and high-voltage programming.

1:10:00 Hot-Electron Injection Efficiency and the Next Lecture

A large drain voltage, around 6 volts, accelerates channel electrons; a small fraction gain enough kinetic energy to cross the tunnel-oxide barrier into the floating gate.
The gate current is tiny compared with drain current, giving a hot-electron programming efficiency of roughly 10^-6 to 10^-8.
Yu concludes with split-gate design as the topic for the next lecture.

Summary, takeaways, and chapters were generated by AI from the video's transcript and may contain errors. The video belongs to its creator, Shimeng Yu.